1. Field of the Invention
The present invention relates to a serial transmission technique using a plurality of serial transmission paths.
2. Description of Related Art
As shown in FIG. 8 as an example, a typical serial interface equipped with multiple lanes such as PCI-Express (registered trademark) includes a parallel-serial conversion circuit 301 in the transmitting unit 101, and two or more serial transmission paths 304, 305, 306 and 307 used to transmit converted data. Further, the serial interface also includes a deskew circuit 302 that corrects skew occurring in each of the serial transmission paths 304, 305, 306 and 307 due to the condition and/or the design error of the serial transmission paths 304, 305, 306 and 307 (hereinafter referred to as “inter-lane skew”), and a serial-parallel conversion circuit 303 that converts received serial data into parallel data in the receiving unit 102.
In the serial interface shown in FIG. 8, parallel data is converted into serial data by the parallel-serial conversion circuit 301 of the data transmitting unit 201 in the transmitting unit 101. The converted serial data is transmitted to the receiving unit 102 through the serial transmission paths 304, 305, 306 and 307. After that, the transmitted serial data is corrected for the inter-lane skew by the deskew circuit 302 of the data receiving unit 202. The serial data that is corrected by and output from the deskew circuit 302 is converted into parallel data by the serial-parallel conversion circuit 303 and the converted parallel data is externally output.
As described above, the inter-lane skew occurs between the serial transmission paths 304, 305, 306 and 307, which extend from the transmitting unit 101 to the receiving unit 102. The deskew circuit 302 performs waiting for transmission data in order to correct the transmitted data for the inter-lane skew. This waiting process is necessary to restore the serial data, which was converted by the parallel-serial conversion circuit 301, to the original parallel data by the serial-parallel conversion circuit 303.
Published Japanese Translation of PCT International Publication for Patent Application, No. 2009-525625 discloses an embodiment of a transmission technique using multiple high-speed serial data paths. In this embodiment, packets to be transmitted through each lane is determined based on the inter-lane skew and the size of the packet on the transmission side, and then the determined packets are transmitted through each lane in a full-packet state (in the case of typical serial transmission, packets are divided for each lane and transmitted through each lane). According to the literature, this configuration eliminates the need for the deskew buffer on the reception side.
In the above-described serial interface shown in FIG. 8, the countermeasures against the inter-lane skew, which occurs when data is transmitted from the transmitting unit 101 to the receiving unit 102, are taken only on the receiving unit 101 side. Therefore, the waiting needs to be performed until all the data are received on the receiving unit 102 side, thus causing a problem that the latency, which is determined by the lane having the largest inter-lane skew, increases.
The embodiment disclosed in Published Japanese Translation of PCT International Publication for Patent Application, No. 2009-525625 also cannot solve the above-described problem regarding the increase in latency.